An electronic device or communication device performs data communication in synchronization with a clock signal. Therefore, it is important to generate a clock signal having an accurate frequency and phase for high-speed data communication.
In general, a PLL is widely used to synthesize a frequency. The PLL may be roughly divided into two kinds of PLLs depending on a design method. One is an analog PLL based on an early analog design method, and the other is a digital PLL based on a digital design method.
FIG. 1A is a block diagram of an analog PLL according to a related art. As illustrated in FIG. 1A, the PLL 100 includes a PD (Phase Detector) 110, an LF (Loop Filter) 120, a VCO (Voltage-Controlled Oscillator) 130 and a divider 140.
FIG. 1B is a waveform diagram of each unit in the PLL 100. Referring to FIG. 1B, an operation of the PLL 100 will be described as follows.
The PD 110 compares the phases of a reference clock signal REF and a divided signal DIV, and generates an error signal UP and DN based on a phase difference between the reference clock signal REF and the divided signal DIV. The LF 120 outputs a filtering voltage V by filtering the error signal UP and DN. The VCO 130 generates an output signal OUT having a frequency which is adjusted according to the filtering voltage V. The divider 140 generates the divided signal DIV by dividing the output signal OUT at a preset division ratio of 4, for example. The divider 140 may be implemented as a fractional-N divider or integer-N divider.
However, such an analog PLL is very sensitive to a PVT (Process, Voltage, Temperature) variation, has high power consumption, and occupies a large installation area.
In order to compensate for such a disadvantage, the digital PLL has been suggested.
FIG. 2 is a block diagram illustrating an ADPLL (All-Digital PLL) according to a related art. As illustrated in FIG. 2, the PLL 200 includes a TDC (Time to Digital Converter) 210, a DLF (Digital Loop Filter) 220, a DCO (Digitally Controlled Oscillator) 230 and a divider 240.
Like the analog PLL, the digital PLL requires phase comparison between the reference clock signal REF and the divided signal DIV. The analog PLL outputs a phase difference as a voltage or current. In the digital PLL, however, the TDC 210 converts a phase difference between the reference clock signal REF and the divided signal DIV, that is, a time difference into a digital code DTDC, and outputs the digital code DTDC.
The DLF 220 generates a digital code DDLF by filtering the digital code generated through the TDC 210 using an adder and a multiplexer.
The DCO 230 generates an output signal OUT whose phase and frequency are adjusted according to the digital code DDLF outputted from the DLF 220.
The divider 240 generates the divided signal DIV by dividing the output signal OUT. The divider 240 may be implemented as a fractional-N divider or integer-N divider.
Such a digital PLL 200 has an installation area and power consumption that are much smaller than the analog PLL 100, and is relatively insensitive to a PVT variation.
Recently, with the development of a semiconductor fabrication process, the unit lengths of semiconductor elements have gradually scaled down. The scale-down of the fabrication process has significantly improved the integration density and performance (speed and power consumption) of circuits, but exponentially increased the number of design rule constraints (DRC) that a designer needs to consider. Thus, as a design cost (effort and time) is rapidly increased, research is actively being conducted on an all-synthesizable circuit capable of significantly reducing the design cost by considerably shortening design and verification time.
The linearity and resolution of the DCO and the TDC which are used in the digital PLL decide the performance of a frequency synthesizer. Thus, the digital PLL needs to be verified through a mixed signal simulation. In this case, the digital PLL requires almost the same verification time and effort as the analog PLL. Therefore, the portability of design, which is an advantage of the digital design, may be limited to a specific portion.